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features q 20mhz 16-bit microcontroller compatible with industry standard?s mcs-96 isa - register to register architecture - 1000 byte register ram q three 8-bit i/o ports q on-board interrupt controller q three pulse-width modulated outputs q high speed i/o q uart serial port q dedicated baud rate generator q software and hardware timers - 16-bit watchdog timer, four 16-bit software timers - three 16-bit counter/timers q error detection and correction for external memory accesses q qml q compliant part q standard microcircuit drawing 5962-98583 introduction the ut80c196kd is compatible with industry standard?s mcs-96 instruction set. the ut80c196kd is supported by commercial hardware and software development tools. the ut80c196kd accesses instruction code and data via a 16-bit address and data bus. the 16-bit bus allows the microcontroller to access 128k bytes of instruction/data memory. integrated software and hardware timers, high speed i/o, pulse width modulation circuitry, and uart make the ut80c196kd ideal for control type applications. the cpu?s alu supports byte and word adds and subtracts, 8 and 16 bit multiplies, 32/16 and 16/8 bit divides, as well as increment, decrement, negate, compare, and logical operations. the ut80c196kd?s interrupt controller prioritizes and vectors 18 interrupt events. interrupts include normal interrupts and special interrupts. to reduce power consumption, the microcontroller supports software invoked idle and power down modes. the ut80c196kd is packaged in a 68-lead quad flatpack. 1000 bytes ram register file alu microcode engine interrupt controller pts memory controller queue watchdog timer pwm port2 serial port hsio and timers hsi hso alternate functions cpu alternate functions port1 hold hlda breq pwm1 pwm2 control signals address /data bus figure 1. ut80c196kd microcontroller f i r s t p a s s c o r e i p port0 extint ecb0- ecb5 standard products ut80c196kd microcontroller datasheet september 2002
2 1.0 signal description port 0 (p0.0 - p0.7): port 0 is an 8-bit input only port when used in its default mode. when configured for their alternate function, five of the bits are bi-directional edac check bits as shown in table 1. port 1 (p1.0 - p1.7): port 1 is an 8-bit, quasi-bidirectional, i/o port. all pins are quasi-bidirectional unless the alternate function is selected per table 2. when the pins are configured for their alternate functions, they act as standard i/o, not quasi- bidirectional. port 2 (p2.0 - p2.7): port 2 is an 8-bit, multifunctional, i/o port. these pins are shared with timer 2 functions, serial data i/o and pwm0 output, per table 3. ad0-ad7: the lower 8-bits of the multiplexed address/data bus. the pins on this port are bidirectional during the data phase of the bus cycle. ad8-ad15: the upper 8-bits of the multiplexed address/data bus. the pins on this port are bidirectional during the data phase of the 16-bit bus cycle. when running in 8-bit bus width, these pins are non-multiplexed, dedicated upper address bit outputs. hsi: inputs to the high speed input unit. four hsi pins are available: hsi.0, hsi.1, hsi.2, and hsi.3. two of these pins (hsi.2 and hsi.3) are shared with the hso unit. two of these pins (hsi.0 and hsi.1) have alternate functions for timer 2. hso: outputs from the high speed output unit. six hso pins are available: hso.0, hso.1, hso.2, hso.3, hso.4, and hso.5. pins hso.4 and hso.5 are shared with pins hsi.2 and hsi.3 of the hsi unit respectively. table 1. port 0 alternate functions port pin alternate name alternate function p0.0-p0.3, p0.6 ecb0-ecb4 error detection & correction check bits p0.4 p0.5 input port pins p0.7 extint setting ioc1.1=1 will allow p0.7 to be used for extint (int07) table 2. port 1 alternate functions port pin alternate name alternate function p1.0 p1.0 i/o pin p1.1 p1.1 i/o pin p1.2 p1.2 i/o pin p1.3 pwm1 setting ioc3.2=1 enables p1.3 as the pulse width modulator (pwm1) output pin. p1.4 pwm2 setting ioc3.3=1 enables p1.4 as the pulse width modulator (pwm2) output pin. p1.5 breq bus request, output activated when the bus controller has a pending external memory cycle. p1.6 hlda bus hold acknowledge, output indicating the release of the bus. p1.7 hold bus hold, input requesting control of the bus. table 3. port 2 alternate functions port pin alternate name alternate function p2.0 txd transmit serial data. p2.1 rxd receive serial data. p2.2 extint external interrupt. clearing ioc1.1 will allow p2.2 to be used for extint (int07) p2.3 t2clk timer 2 clock input and serial port baud rate generator input. p2.4 t2rst timer 2 reset p2.5 pwm0 pulse width modulator output 0 p2.6 t2up-dn controls the direction of the timer 2 counter. logic high equals count down. logic low equals count up. p2.7 t2capture a rising edge on p2.7 causes the value of timer 2 to be captured into this register, and generates a timer 2 capture interrupt (int11).
3 1.1 hardware interface 1.1.1 interfacing with external memory the ut80c196kd can interface with a variety of external memory devices. it supports either a fixed 8-bit bus width or a dynamic 8-bit/16-bit bus width, internal ready control for slow external memory devices, a bus-hold protocol that enables external devices to take over the bus, and several bus-control modes. these features provide a great deal of flexibility when interfacing with external memory devices. 1.1.1.1 chip configuration register the chip configuration register (ccr) is used to initialize the ut80c196kd immediately after reset. the ccr is fetched from external address 2018h (chip configuration byte) after removal of the reset signal. the chip configuration byte (ccb) is read as either an 8-bit or 16-bit word depending on the value of the buswidth pin. the composition of the bits in the ccr are shown in table 4. there are 8 configuration bits available in the ccr. however, bits 7 and 6 are not used by the ut80c196kd. bits 5 and 4 comprise the ready mode control which define internal limits for waitstates generated by the ready pin. bit 3 controls the definition of the ale/ adv pin for system memory controls while bit 2 selects between the different write modes. bit 1 selects whether the ut80c196kd will use a dynamic 16-bit bus or whether it will be locked in as an 8-bit bus. finally, bit 0 enables the power down mode and allows the user to disable this mode for protection against inadvertent power downs. 1.1.1.2 bus width and memory configurations the ut80c196kd external bus can operate as either an 8-bit or 16-bit multiplexed address/data bus (see figure 2) . the value of bit 1 in the ccr determines the bus operation. a logic low value on ccr.1 locks the bus controller in 8-bit bus mode. if, however, ccr.1 is a logic high, then the buswidth signal is used to decide the width of the bus. the bus is 16 bits wide when the buswidth signal is high, and is 8 bits when the buswidth signal is low. 1.1.2 reset to reset the ut80c196kd, hold the reset pin low for at least 16 state times after the power supply is within tolerance and the oscillator has stabilized. resets following the power-up reset may be asserted for at least one state time, and the device will turn on a pull-down transistor for 16 state times. this enables the reset signal to function as the system reset. the reset state of the external i/o is shown in table 9 , and the register reset values are shown in table 8. 1.1.3 instruction set the instruction set for the ut80c196kd is compatible with the industry standard mcs-96 instruction set used on the 80c196kd. notes: 1.the first instruction read following reset will be from location 2080h. all other external memory can be used as instruction and/or data memory. table 4. chip configuration register bit function 7 n/a 6 n/a 5 irc1 - internal ready mode control 4 irc0 - internal ready mode control 3 address valid strobe select (ale/ adv ) 2 write strobe mode select ( wr and bhe / wrl and wrh ) 1 dynamic bus width enable 0 enable power down mode table 5. memory map memory description begin end external memory 1 02080h 0ffffh reserved 0205eh 0207fh pts vectors 02040h 0205dh upper interrupt vectors 02030h 0203fh reserved 02020h 0202fh reserved 02019h 0201fh chip configuration byte 02018h 02018h reserved 02014h 02017h lower interrupt vectors 02000h 02013h external memory 00400h 1fffh internal memory (ram) 0001ah 003ffh special function registers 00000h 00019h
4 table 6. interrupt vector sources, locations, and priorities number interrupt vector source(s) interrupt vector location pts vector location priority 1 (0 is the lowest priority) special unimplemented opcode unimplemented opcode 2012h n/a n/a special software trap software trap 2010h n/a n/a int 15 nmi 2 nmi 203eh n/a 15 int 14 hsi fifo full hsi fifo full 203ch 205ch 14 int 13 extint 1 2 port 2.2 203ah 205ah 13 int 12 timer 2 overflow timer 2 overflow 2038h 2058h 12 int 11 timer 2 capture 2 timer 2 capture 2036h 2056h 11 int 10 hsi fifo 4 hsi fifo fourth entry 2034h 2054h 10 int 9 receive ri flag 3 2032h 2052h 9 int 8 transmit ti flag 3 2030h 2050h 8 int 7 extint 2 port 2.2 or port 0.7 200eh 204eh 7 int 6 serial port ri flag and ti flag 4 200ch 204ch 6 int 5 software timer software timer 0-3 timer 2 reset 200ah 204ah 5 int 4 hsi.0 2 hsi.0 pin 2008h 2048h 4 int 3 high speed outputs events on hso.0 thru hso.5 lines 2006h 2046h 3 int 2 hsi data available hsi fifo full or hsi holding reg. loaded 2004h 2044h 2 int 1 edac bit error single bit error single bit error ovf double bit error 2002h 2042h 1 int 0 timer overflow timer 1 or timer 2 2000h 2040h 0 all of the previous maskable interrupts can be assigned to the pts. any pts interrupt has priority over all other maskable interrupts.
5 notes: 1. the unimplemented opcode and software trap interrupts are not prioritized. the interrupt controller immediately services these interrupts when they are asserted. nmi has the highest priority of all prioritized interrupts. any pts interrupt has priority over lower priority intte rupts, and over all other maskable interrupts. the standard maskable interrupts are serviced according to their priority number with int0 has the lowest priority of all interrupts. 2. these interrupts can be configured to function as independant, external interrupts. 3. if the serial interrupt is masked and the receive and transmit interrupts are enabled, the ri flag and ti flag generate separate receive and transmit inter- rupts. 4. if the receive and transmit interrupts are masked and the serial interrupt is enabled, both ri flag and ti flag generate a seria l port interrupt.
6 notes: 1. for some functions that share a register address in hwindow0, the opposite access type (read/write) is available in hwindow 1 5 if indicated by the three asterisks (***). 2. these registers are not available in the industry standard 80c196kd. therefore, industry standard development software will n ot recognize these mnemonics, and you will only be able to access them via their physical addresses. table 7. sfr memory mapping address hwin 0 read hwin 0 write hwin 1 hwin 15 1 019h stack pntr (hi) stack pntr (hi) stack pntr (hi) stack pntr (hi) 018h stack pntr (lo) stack pntr (lo) stack pntr (lo) stack pntr (lo) 017h ios2 pwm0_ctrl pwm2_ctrl *** 016h ios1 ioc1 pwm1_ctrl *** 015h ios0 ioc0 edac-cs 2 *** 014h wsr wsr wsr wsr 013h int_mask1 int_mask1 int_mask1 int_mask1 012h int_pend1 int_pend1 int_pend1 int_pend1 011h sp_stat sp_con reserved *** 010h port 2 port 2 reserved psw 2 00fh port 1 port 1 timer 3(hi) 2 reserved 00eh port 0 baud rate timer 3(lo) 2 reserved 00dh timer 2 (hi) timer 2 (hi) wdt-scale 2 t2capture (hi) 00ch timer 2 (lo) timer 2 (lo) ioc3 t2capture (lo) 00bh timer 1 (hi) ioc2 int_pri(hi) 2 *** 00ah timer 1 (lo) watchdog int_pri(lo) 2 *** 009h int_pend int_pend int_pend int_pend 008h int_mask int_mask int_mask int_mask 007h sbuf (rx) sbuf (tx) ptssrv (hi) *** 006h hsi_status hso_command ptssrv (lo) *** 005h hsi_time(hi) hso_time (hi) ptssel (hi) *** 004h hsi_time (lo) hso_time (lo) ptssel (lo) *** 003h reserved hsi_mode reserved *** 002h reserved reserved reserved reserved 001h zero_reg (hi) zero_reg (hi) zero-reg (hi) zero_reg (hi) 000h zero_reg (lo) zero_reg (lo) zero_reg (lo) zero_reg (lo)
7 table 8: special function register reset values internal register binary reset state hexadecimal reset value stack pointer (sp) xxxx xxxx xxxx xxxx xxxx i/o status register 2 (ios2) 0000 0000 00 i/o status register 1 (ios1) 0000 0000 00 i/o status register 0 (ios0) 0000 0000 00 window select register (wsr) 0000 0000 00 interrupt mask register 1 (int_mask1) 0000 0000 00 interrupt pending register 1 (int_pend1) 0000 0000 00 serial port status register (sp_stat) 0000 1011 0b port 2 register (port2) 110x xxx1 xx port 1 register (port1) 1111 1111 ff port 0 register (port0) xxxx xxxx xx timer 2 value register (timer2) 0000 0000 0000 0000 0000 timer 1 value register (timer1) 0000 0000 0000 0000 0000 interrupt pending register (int_pend) 0000 0000 00 interrupt mask register (int_mask) 0000 0000 00 receive serial port register (sbuf (rx)) 0000 0000 00 hsi status register (hsi_status) x0x0 x0x0 xx hsi time register (hsi_time) xxxx xxxx xxxx xxxx xxxx zero register (zero_reg) 0000 0000 0000 0000 0000 pwm0 control register (pwm0_ctrl) 0000 0000 00 i/o control register 1 (ioc1) 0010 0001 21 i/o control register 0 (ioc0) 0000 00x0 0x serial port control register (sp_con) 0000 1011 0b baud rate register (baud_rate) 0000 0000 0000 0001 0001 i/o control register 2 (ioc2) x00x x000 xx watch dog timer register (watch- dog) 0000 0000 00
8 transmit serial port buffer (sbuf (tx)) 0000 0000 00 hso command register (hso_command) 0000 0000 00 hso time register (hso_time) 0000 0000 0000 0000 0000 hsi mode register (hsi_mode) 1111 1111 ff pwm2 control register (pwm2_ctrl) 0000 0000 00 pwm1 control register (pwm1_ctrl) 0000 0000 00 edac control and status register (edac_cs) 0000 0000 00 timer 3 value register (timer3) 0000 0000 0000 0000 0000 watchdog timer prescaler (wdt_scale) 0000 0000 00 i/o control register 3 (ioc3) 1111 0000 f0 interrupt priority register (int_pri) 0000 0000 00 pts service register (ptssrv) 0000 0000 0000 0000 0000 pts select register (ptssel) 0000 0000 0000 0000 0000 timer 2 capture register (t2capture) 0000 0000 0000 0000 0000 program counter (pc) 0010 0000 1000 0000 2080 chip configuration register (ccr) xx10 1111 xf table 8: special function register reset values internal register binary reset state hexadecimal reset value
9 table 9 : external i/o reset state external i/o i/o function after reset i/o state during reset i/o state after reset address/data bus (ad15:0) address/data bus pulled high driven output ale adv ale pulled high driven output rd rd pulled high driven output wr wrl wr pulled high driven output port 0 (p0.0-p0.3; p0.6) ecb(4:0) [p0.0-p0.3; p0.6] and ecb(4:0) undefined inputs 1 undefined i/o 1, 2 port 0 (p0.4 and p0.5) p0.4 and p0.5 undefined inputs 1 undefined inputs 1 port 0 (p0.7) extint p0.7 undefined input 1 undefined input 1 nmi nmi pulled down pulled down hsi.0 t2rst hsi.0 disabled input 1 disabled input 1 hsi.1 t2clk hsi.1 disabled input 1 disabled input 1 hsi.2/hso.4 undefined disabled i/o 1 disabled i/o 1 hsi.3/hso.5 undefined disabled i/o 1 disabled i/o 1 hso.0 through hso.3 hso.0-hso.3 pulled down driven low outputs port 1 (p1.0-p1.7) pwm1; pwm2; breq ; hlda ; hold p1.0-p1.7 pulled up pulled up port 2 (p2.0) txd txd pulled up driven high output port 2 (p2.1) rxd rxd undefined input 1 undefined input 1 port 2 (p2.2) extint p2.2 and extint undefined input 1 undefined input 1 port 2 (p2.3) t2clk p2.3 and t2clk undefined input 1 undefined input 1 port 2 (p2.4) t2rst p2.4 undefined input 1 undefined input 1
10 notes: 1. these pins must not be left floating. input voltages must not exceed v dd during power-up. 2. do not directly tie these pins to v dd or gnd; if edacen goes low, they may be driven by the ut80c196kd and bus contention may occur. port 2 (p2.5) pwm0 pwm0 pulled down driven low output port 2 (p2.6) t2up-dn p2.6 pulled up pulled up port 2 (p2.7) t2capture p2.7 and t2capture pulled up pulled up edacen edacen undefined input 1 undefined input 1 ecb5 ecb5 undefined i/o 1 undefined i/o 1,2 ready ready undefined input 1 undefined input 1 buswidth buswidth undefined input 1 undefined input 1 bhe wrh bhe pulled up driven output clkout clkout driven output driven output inst inst pulled down driven output reset reset pulled low by system pulled up table 9 : external i/o reset state external i/o i/o function after reset i/o state during reset i/o state after reset
11 ut80c196kd ut80c196 kd bus control 16-bit multiplexed address/data 8-bit multiplexed address/data 8-bit latched address high bus control ad0-ad15 ad0-ad7 ad8-ad15 16-bit bus 8-bit bus figure 2. bus width options
12 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 9 8 7 6 5 4 3 2 1 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 ut80c196kd top view figure 3. 68-pin quad flatpack package ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 p2.3/t2clk h s i . 3 / h s o . 5 h s 0 . 0 h s 0 . 1 b r e q / p 1 . 5 h l d a / p 1 . 6 h o l d / p 1 . 7 t 2 u p - d n / p 2 . 6 h s 0 . 2 h s 0 . 3 v s s e d a c e n t 2 c a p t u r e / p 2 . 7 p w m 0 / p 2 . 5 w r / w r l b h e / w r h t 2 r s t / p 2 . 4 r e a d y p 0 . 7 / e x t i n t p 0 . 6 / e c b 0 p 0 . 2 / e c b 1 p 0 . 0 / e c b 2 p 0 . 1 / e c b 3 p 0 . 3 / e c b 4 n m i e c b 5 v d d v s s x t a l 1 v s s c l k o u t b u s w i d t h i n s t a l e / a d v r d 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 p0.5 p0.4 v ss v dd v ss extint/p2.2 reset rxd/p2.1 txd/p2.0 p1.0 p1.1 p1.2 pwm1/p1.3 pwm2/p1.4 t2rst/hsi.0 t2clk/hsi.1 hsi.2/hs0.4
13 legend for i/o fields: to = ttl compatible output ti = ttl compatible input ci = cmos only input tuo = ttl compatible output (internally pulled high) tdo = ttl compatible output (internally pulled low) tui = ttl compatible input (internally pulled high) tdi = ttl compatible input (internally pulled low) tb = ttl compatible bidirectional tuq = ttl compatible quasi-bidirectional (internally pulled high) tub = ttl compatible bidirectional (internally pulled high) tubs = ttl compatible bidirectional schmitt trigger (internally pulled high) pwr = +5v (v dd ) gnd = ov (v ss ) table 10: 68-lead flat pack pin descriptions qfp pin# i/o name active description 1 pwr v dd --- digital supply voltage (+5v). there are 2 v dd pins, both of which must be connected. 2 tb ecb5 1 --- edac check bit 5. asserting the edacen pin will cause the error detection and correction engine to pass the edac check bit 5 through pin 2 of the ut80c196kd. 3 tdi nmi high non-maskable interrupt. a positive transition causes a vector through the nmi interrupt at location 203eh. assert nmi for at least 1 state time to guarantee acknowledgment by the interrupt controller. 4 ti p0.3 --- port 0 pin 3. an input only port pin that is read at location 0eh in hwindow 0. tb ecb4 1 --- edac check bit 4. asserting the edacen pin will cause the error detection and correction engine to pass the edac check bit 4 through pin 4 of the ut80c196kd. 5 ti p0.1 --- port 0 pin 1. an input only port pin that is read at location 0eh in hwindow 0. tb ecb3 1 --- edac check bit 3. asserting the edacen pin will cause the error detection and correction engine to pass the edac check bit 3 through pin 5 of the ut80c196kd. 6 ti p0.0 --- port 0 pin 0. an input only port pin that is read at location 0eh in hwindow 0. tb ecb2 1 --- edac check bit 2. asserting the edacen pin will cause the error detection and correction engine to pass the edac check bit 2 through pin 6 of the ut80c196kd.
14 7 ti p0.2 --- port 0 pin 2. an input only port pin that is read at location 0eh in hwindow 0. tb ecb1 1 --- edac check bit 1. asserting the edacen pin will cause the error detection and correction engine to pass the edac check bit 1 through pin 7 of the ut80c196kd. 8 ti p0.6 --- port 0 pin 6. an input only port pin that is read at location 0eh in hwindow 0. tb ecb0 1 --- edac check bit 0. asserting the edacen pin will cause the error detection and correction engine to pass the edac check bit 0 through pin 8 of the ut80c196kd. 9 ti p0.7 --- port 0 pin 7. an input only port pin that is read at location 0eh in hwindow 0. ti extint high external interrupt. setting ioc1.1 = 1 enables pin 9 as the source for the external interrupt extint. a rising edge on this pin will generate extint (int07, 200eh). assert extint for at least 2 state times to ensure acknowledgment by the interrupt controller. during power down mode, asserting extint places the chip back into normal operation, even if extint is masked. 10 ti p0.5 --- port 0 pin 5. an input only port pin that is read at location 0eh in hwindow 0. 11 ti p0.4 --- port 0 pin 4. an input only port pin that is read at location 0eh in hwindow 0. 12 gnd v ss --- digital circuit ground (0v). there are 4 v ss pins, all of which must be connected and one additional recommeded v ss connec- tion. 13 pwr v dd --- digital supply voltage (+5v). there are 2 v dd pins, both of which must be connected. 14 gnd v ss --- digital circuit ground (0v). there are 4 v ss pins, all of which must be connected and one additional recommeded v ss connec- tion. table 10: 68-lead flat pack pin descriptions qfp pin# i/o name active description
15 15 ti p2.2 --- port 2 pin 2. an input only port pin that is written at location 10h of hwindow 0. p2.2 will always generate extint1 (int13, 203ah) unless masked by the int_mask1 register. assert extint1 for at least 2 state times to guarantee acknowl- edgment by the interrupt controller. ti extint high external interrupt. setting ioc1.1 = 0 enables pin 15 as the source for the external interrupt extint. a rising edge on this pin will generate extint (int07, 200eh). assert extint for at least 2 state times to ensure acknowledgment by the interrupt controller. during power down mode, asserting extint places the chip back into normal operation, even if extint is masked. 16 tubs reset low master reset. the first external reset signal supplied to the ut80c196kd must be active for at least 16 state times. all subsequent reset assertions need only be active for 1 state time because the ut80c196kd will continue driving the reset signal for an additional 16 state times. see section 1.1.2 for more information on the reset function of the ut80c196kd. 17 ti p2.1 --- port 2 pin 1. an input only port pin that is read at location 10h of hwindow 0. setting spcon.3 = 0 enables the p2.1 function of pin 17. tb rxd --- rxd is a bidirectional serial data port. when operating in serial modes 1, 2, and 3, rxd receives serial data. when using serial mode 0, rxd operates as an input and an open-drain output for data. setting spcon.3 = 1 enables the rxd function of pin 17. 18 2 tuo p2.0 --- port 2 pin 0. an output only port pin that is written at location 10h of hwindow 0. setting ioc1.5 = 0 enables the p2.0 function of pin 18. tuo txd --- transmit serial data (txd). when set to serial mode 1, 2, or 3, txd transmits serial port data. when using serial mode 0, txd is used as the serial clock output. setting ioc1.5 = 1 enables the txd function of pin 18. tui ict low in-circuit test. the ut80c196kd will enter the in-circuit test mode if this pin is held low during the rising edge of reset . table 10: 68-lead flat pack pin descriptions qfp pin# i/o name active description
16 19 tuq p1.0 --- port 1 pin 0. a quasi-bidirectional port pin that is read and writ- ten at location 0fh of hwindow 0. 20 tuq p1.1 --- port 1 pin 1. a quasi-bidirectional port pin that is read and writ- ten at location 0fh of hwindow 0. 21 tuq p1.2 --- port 1 pin 2. a quasi-bidirectional port pin that is read and writ- ten at location 0fh of hwindow 0. 22 tuq p1.3 --- port 1 pin 3. a quasi-bidirectional port pin that is read and writ- ten at location 0fh of hwindow 0. setting ioc3.2 = 0 enables the p1.3 function of pin 22. tuo pwm1 --- pulse width modulator (pwm) output 1. the output signal will be a waveform whose duty cycle is programmed by the pwm1_control register, and the frequency is selected by ioc2.2. setting ioc3.2 = 1 enables the pwm1 function of pin 22. 23 tuq p1.4 --- port 1 pin 4. a quasi-bidirectional port pin that is read and writ- ten at location 0fh of hwindow 0. setting ioc3.3 = 0 enables the p1.4 function of pin 23. tuo pwm2 --- pulse width modulator (pwm) output 2. the output signal will be a waveform whose duty cycle is programmed by the pwm2_control register, and the frequency is selected by ioc2.2. setting ioc3.3 = 1 enables the pwm2 function of pin 23. 24 ti hsi.0 --- high speed input module, input pin 0. unless masked, a rising edge on this input will generate the hsi.0 pin interrupt (int04, 2008h). assert the hsi.0 pin for at least 2 state times to ensure acknowledgment by the interrupt controller. setting ioc0.0 = 1 enables pin 24 as an hsi input, and allows events on this pin to be loaded into the hsi fifo. ti t2rst high timer 2 reset. a rising edge on the t2rst pin resets timer 2. to enable the t2rst function of pin 24, set ioc0.3 = 1 and ioc0.5 = 1. table 10: 68-lead flat pack pin descriptions qfp pin# i/o name active description
17 25 ti hsi.1 --- high speed input module, input pin 1. setting ioc0.2 = 1 enables pin 25 as an hsi input, and allows events on this pin to be loaded into the hsi fifo. ti t2clk --- timer 2 clock. setting ioc0.7 = 1 and ioc3.0 = 0 enables pin 25 to function as the timer 2 clock source. 26 to hso.4 --- high speed output module, output pin 4. this pin can simulta- neously operate in the hsi and hso modes of operation. as a result, this pin acts as an output that the hsi monitors. setting ioc1.4 = 1 enables the hso.4 function of pin 26. ti hsi.2 --- high speed input module, input pin 2. this pin can simulta- neously operate in the hsi and hso modes of operation. as a result, this pin can monitor events on the hso. setting ioc0.4 = 1 enables pin 26 as an hsi input pin, and allows events on this pin to be loaded into the hsi fifo. 27 to hso.5 --- high speed output module, output pin 5. this pin can simulta- neously operate in the hsi and hso modes of operation. as a result, this pin acts as an output that the hsi monitors. setting ioc1.6 = 1 enables the hso.5 function of pin 27. ti hsi.3 --- high speed input module, input pin 3. this pin can simulta- neously operate in the hsi and hso modes of operation. as a result, this pin can monitor events on the hso. setting ioc0.6 = 1 enables pin 27 as an hsi input pin, and allows events on this pin to be loaded into the hsi fifo. 28 tdo hso.0 --- high speed output module, output pin 0. the hso.0 pin is a dedicated output for the hso module. 29 tdo hso.1 --- high speed output module, output pin 1. the hso.1 pin is a dedicated output for the hso module. table 10: 68-lead flat pack pin descriptions qfp pin# i/o name active description
18 30 tuq p1.5 --- port 1 pin 5. a quasi-bidirectional port pin that is read and writ- ten at location 0fh of hwindow 0. setting wsr.7 = 0 enables the p1.5 function of pin 30. tuo breq low bus request. the breq output signal asserts during a hold cycle when the internal bus controller has a pending external memory cycle. during a hold cycle, breq will not be asserted until the hlda signal is asserted. once asserted, breq does not deas- sert until the hold signal is released. setting wsr.7 = 1 enables the breq function of pin 30. 31 2 tuq p1.6 --- port 1 pin 6. a quasi-bidirectional port pin that is read and writ- ten at location 0fh of hwindow 0. setting wsr.7 = 0 enables the p1.6 function of pin 31. tuo hlda low bus hold acknowledge. the ut80c196kd asserts the hlda signal as a result of another device activating the hold signal. by asserting this signal, the ut80c196kd is indicating that it has released the bus. setting wsr.7 = 1 enables the hlda function of pin 31. 32 tuq p1.7 --- port 1 pin 7. a quasi-bidirectional port pin that is read and writ- ten at location 0fh of hwindow 0. setting wsr.7 = 0 enables the p1.7 function of pin 32. tui hold low bus hold. the hold signal is used to request control of the bus by another dma device. setting wsr.7 = 1 enables the hold function of pin 32. 33 tuq p2.6 --- port 2 pin 6. a quasi-bidirectional port pin that is read and writ- ten at location 10h of hwindow 0. setting ioc2.1 = 0 enables the p2.6 function of pin 33. tui t2up-dn --- timer 2 up or down. the t2up-dn pin will dynamically change the direction that timer 2 counts. t2up-dn = 1 then timer 2 counts down. t2up-dn = 0 then timer 2 counts up. setting ioc2.1 = 1 enables the t2up-dn function of pin 33. when ioc2.1 = 0, timer 2 will only count up. table 10: 68-lead flat pack pin descriptions qfp pin# i/o name active description
19 34 tdo hso.2 --- high speed output module, output pin 2. the hso.2 pin is a dedicated output for the hso module. 35 tdo hso.3 --- high speed output module, output pin 3. the hso.3 pin is a dedicated output for the hso module. 36 gnd v ss --- digital circuit ground (0v). there are 4 v ss pins, all of which must be connected and one additional recommeded v ss connec- tion. 37 ti edacen low edac enable. asserting the edacen signal activates the error detection and correction engine. this causes the ut80c196kd to include ecb(5:0) as the edac check bit pins in all external memory cycles. 38 tuq p2.7 --- port 2 pin 7. a quasi-bidirectional port pin that is read and writ- ten at location 10h of hwindow 0. tuq t2capture high timer 2 capture. a rising edge on this pin loads the value of timer 2 into the t2capture register, and generates a timer 2 capture interrupt (int11, 2036h). assert the t2capture sig- nal for at least 2 state times to guarantee acknowledgment by the interrupt controller. using int_mask1.3 controls whether or not a rising edge causes an interrupt. 39 tdo p2.5 --- port 2 pin 5. an output only port pin that is written at location 10h of hwindow 0. setting ioc1.0 = 0 enables the p2.5 function of pin 39. tdo pwm0 --- pulse width modulator (pwm) output 0. the output signal will be a waveform whose duty cycle is programmed by the pwm0_control register, and the frequency is selected by ioc2.2. setting ioc1.0 = 1 enables the pwm0 function of pin 39. 40 2 tuo wr low write. the wr signal indicates that an external write is occur- ring. activation of this signal only occurs during external mem- ory writes. setting ccr.2 = 1 enables the wr function of pin 40. tuo wrl low write low. the wrl signal is activated when writing the low byte of a 16-bit wide word, and is always asserted for 8-bit wide memory writes. setting ccr.2 = 0 enables the wrl function of pin 40. table 10: 68-lead flat pack pin descriptions qfp pin# i/o name active description
20 41 tuo bhe low byte high enable. the assertion of the bhe signal will occur for all 16-bit word writes, and high byte writes in both 8- and 16- bit wide bus cycles. setting ccr.2 = 1 enables the bhe function of pin 41. tuo wrh low write high. the wrh signal is asserted for high byte writes, and word writes for 16-bit wide bus cycles. additionally, wrh is asserted for all write operations when using an 8-bit wide bus cycle. setting ccr.2 = 0 enables the wrh function of pin 41. 42 ti p2.4 --- port 2 pin 4. an input only port pin that is read at location 10h of hwindow 0. ti t2rst high timer 2 reset. asserting the t2rst signal will reset timer 2. to enable the t2rst function of pin 42, set ioc0.3 = 1 and ioc0.5 = 0. 43 ti ready high ready input. the ready signal is used to lengthen memory cycles by inserting ?wait states? for interfacing to slow peripher- als. when the ready signal is high, no ?wait states? are gener- ated, and the cpu operation continues in a normal fashion. if ready is low during the falling edge of clkout, the mem- ory controller inserts ?wait states? into the memory cycle. ?wait state? generation will continue until a falling edge of clkout detects ready as logically high, or until the number of ?wait states? is equal to the number programmed into ccr.4 and ccr.5. note: the ready signal is only used for external memory accesses, and is functional during the ccr fetch. 44 ti p2.3 --- port 2 pin 3. an input only port pin that is read at location 10h of hwindow 0. ti t2clk --- timer 2 clock input. setting ioc0.7 = 0 and ioc3.0 = 0 enables this pin as the external clock source for timer 2. ioc0.7: ioc3.0: timer 2 clock source: x 1 internal clock source 0 0 p2.3 external clock source 1 0 hsi.1 external clock source 45 tub ad15 --- bit 15 of the address/data bus. this pin is a dedicated address pin when operating with 8-bit wide bus cycles. for 16-bit wide bus cycles, this pin is used as multiplexed address and data. table 10: 68-lead flat pack pin descriptions qfp pin# i/o name active description
21 46 tub ad14 --- bit 14 of the address/data bus. this pin is a dedicated address pin when operating with 8-bit wide bus cycles. for 16-bit wide bus cycles, this pin is used as multiplexed address and data. 47 tub ad13 --- bit 13 of the address/data bus. this pin is a dedicated address pin when operating with 8-bit wide bus cycles. for 16-bit wide bus cycles, this pin is used as multiplexed address and data. 48 tub ad12 --- bit 12 of the address/data bus. this pin is a dedicated address pin when operating with 8-bit wide bus cycles. for 16-bit wide bus cycles, this pin is used as multiplexed address and data. 49 tub ad11 --- bit 11 of the address/data bus. this pin is a dedicated address pin when operating with 8-bit wide bus cycles. for 16-bit wide bus cycles, this pin is used as multiplexed address and data. 50 tub ad10 --- bit 10 of the address/data bus. this pin is a dedicated address pin when operating with 8-bit wide bus cycles. for 16-bit wide bus cycles, this pin is used as multiplexed address and data. 51 tub ad9 --- bit 9 of the address/data bus. this pin is a dedicated address pin when operating with 8-bit wide bus cycles. for 16-bit wide bus cycles, this pin is used as multiplexed address and data. 52 tub ad8 --- bit 8 of the address/data bus. this pin is a dedicated address pin when operating with 8-bit wide bus cycles. for 16-bit wide bus cycles, this pin is used as multiplexed address and data. 53 tub ad7 --- bit 7 of the address/data bus. this pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 54 tub ad6 --- bit 6 of the address/data bus. this pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 55 tub ad5 --- bit 5 of the address/data bus. this pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 56 tub ad4 --- bit 4 of the address/data bus. this pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 57 tub ad3 --- bit 3 of the address/data bus. this pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 58 tub ad2 --- bit 2 of the address/data bus. this pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 59 tub ad1 --- bit 1 of the address/data bus. this pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. 60 tub ad0 --- bit 0 of the address/data bus. this pin is used as multiplexed address and data for both 8- and 16-bit wide bus cycles. table 10: 68-lead flat pack pin descriptions qfp pin# i/o name active description
22 notes: 1. these pins should be pulled high or low when using edac (i.e. edacen = 0) to prevent the voltages on these pins from floating to the switching threshold of the input buffers during long read cycles. 2. these pins must be high on the rising edge of reset in order to avoid entering any test modes. 3. this pin is a recommended v ss connection. the remaining 4 v ss pins are required to be tied to the circuit card ground plane. 61 2 tuo rd low read. the rd signal is an output to external memory that is only asserted during external memory reads. 62 2 tuo ale high address latch enable. the ale signal is an output to external memory that is only asserted during external memory accesses. ale is used to specify that valid address information is avail- able on the address/data bus, and signals the start of a bus cycle. ale is used by an external latch to demultiplex the address from the address/data bus. setting ccr.3 = 1 enables the ale func- tion of pin 62. tuo adv low address valid. the adv signal is an output to external mem- ory that is only asserted during external memory accesses. adv is driven high to specify that valid address information is avail- able on the address/data bus. the adv signal is held low during the data transfer portion of the bus cycle, and is driven high when the bus cycle completes. adv is used by an external latch to demultiplex the address from the address/data bus. setting ccr.3 = 0 enables the adv function of pin 62. 63 tdo inst high instruction fetch. the inst signal indicates the type of external memory cycle being performed. the inst signal will be high during instruction fetches, and will be low for data fetches. note: ccb bytes and interrupt vectors are considered data . 64 ti buswidth --- bus width. the buswidth pin dynamically modifies the width of bus cycles. when a high logic value is supplied, the bus width will be set to 16-bits wide. when a low logic level is supplied, the bus width will be set to 8-bits wide. setting ccr.1 = 1 enables the buswidth pin. setting ccr.1 = 0 disables the buswidth pin. as a result, the ut80c196kd will only perform 8-bit wide bus cycles. 65 tuo clkout --- clock output. the clkout signal is the output of the internal clock. this signal has a 50% duty cycle, and runs at 1/2 the fre- quency of the system clock input to xtal1. setting ioc3.1 = 0 will enable the clkout output signal. 66 gnd v ss 3 --- digital circuit ground (0v). recommended connection for sig- nal integrity improvement. there are 4 v ss pins, all of which must be connected. 67 ci xtal1 --- external oscillator or clock input to the ut80c196kd. the xtal1 input is fed to the on-chip clock generator. 68 gnd v ss --- digital circuit ground (0v). there are 4 v ss pins, all of which must be connected and one additional recommeded v ss connec- tion. table 10: 68-lead flat pack pin descriptions qfp pin# i/o name active description
23 2.0 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recomme nded. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. these ratings are provided as design guidelines. they are not guaranteed by test or characterization. 3. test per mil-std-883, method 1012. symbol parameter limits units v dd dc supply voltage -0.3 to 6.0 v v i/o 2 voltage on any pin -0.3 to v dd +0.3v v t stg storage temperature -65 to +150 c t j maximum junction temperature 175 c q jc thermal resistance, junction-to-case 3 16 c/w i i 2 dc input current 10 ma
24 3.0 dc electrical characteristics ( v dd = 5.0v 10% ) (t c = -55 c to +125 c for "c" screening and -40 c to +125 c for "w" screening) symbol parameter condition minimum maximum unit v il low-level input voltage (except xtal1, reset ) 0.8 v v ih high-level input voltage (except xtal1, reset ) 2.2 v v ih1 high-level input voltage (xtal1) .7v dd v v il1 low-level input voltage (xtal1) .3v dd v v t+ positive going threshold reset .5v dd .7 v dd v v t- negative going threshold reset .2v dd .4 v dd v v h typical range of hysteresis 6 reset .9 v v ol low-level output voltage (cmos load) i ol = 200 m a 6 0.3 v (ttl load) i ol = 4.0ma 0.4 v v oh high-level output voltage 8 (cmos load) (standard outputs) ( ttl load) i oh = -200 m a 6 i oh = -4.0ma v dd -.3 3.8 v v i ohi high-level output current 1 (open drain outputs with pullups) v oh = v dd - .3 6 v oh = v dd - .9 -20 -60 m a m a i il logical 0 input current 2 (test mode entry) v in = v ih -550 -120 m a i li i/o leakage current, standard inputs/outputs in z state v in = v ss or v dd - 5 +5 m a i li1 i/o leakage current, with pullups 3 v in = v ss -800 -150 m a i li2 i/o leakage current, with pulldowns 4 v in = v dd 200 1500 m a c io pin capacitance 6 @ 1mhz, 25 c 15 pf a i dd active power supply current clk@20mhz, typical program flow 110 ma qi dd quiescent power supply current unloaded -55 t o +25 c outputs +125 c 20 1000 m a i ddpd power supply current in power down no active i/o, clk@20mhz 6 m a i ddidle power supply current in idle mode no active i/o, clk@20mhz 55 m a i ddreset power supply current in reset clk @20 mhz, reset < v il 65 ma i os short circuit output current (except for pins listed in note 5) 6,7 v dd = 5.5v -100 130 ma i os1 short circuit output current 5,6,7 v dd = 5.5v -200 250 ma
25 notes: 1. open-drain outputs with pullups include port 1, p2.6 and p2.7. 2. test modes are entered at the reset rising edge by applying v il to one or more of the following pins: txd, rd , wr , hlda . to avoid entering a test mode, ensure that these pins remain above v ih at the rising edge of reset . 3. inputs/outputs with pullup resistors include: reset , port 1, p2.0, p2.6, p2.7, wr , bhe , ad0-15, rd , ale, clkout. 4. inputs/outputs will pulldown resistors include: nmi, hs0.0-hs0.3, p2.5, inst. 5. the i so1 spec applies to pins reset , bhe , rd , clkout. 6. tested only at initial qualification and after any design or process changes which may affect this characteristic. 7. not more than one output may be shorted at a time for maximum duration of one second. 8. for standard outputs not covered by iohi spec.
5.0 ac characteristics read cycle (v dd = 5.0v 10%) (t c = -55 c to +125 c for "c" screening and -40 c to +125 c for "w" screening) symbol parameter minimum maximum unit t avyv 5 address valid to ready setup 2t osc - 30 ns t ylyh 5 non-ready time no upper limit ns t clyx 1,5 ready hold after clkout low 0 2t osc - 20 ns t llyx 1,5 ready hold after ale low t osc 3t osc - 20 ns t avgv 5 address valid to buswidth setup 2t osc - 30 ns t clgx 5 buswidth hold after clkout low 0 ns t avdv 2,5 address valid to input data valid 3t osc - 29 ns t rldv 2 rd active to input data valid 5 (see note 5) t osc - 26 ns t cldv 5 clkout low to input data valid 5 t osc - 26 ns t rhdz 5 end of rd to input data float 0 t osc -10 ns t rxdx 5 data hold after rd inactive 0 t osc -10 ns f osc 5 frequency on xtal1 1 (see note 7) 20 (see note 6) mhz t osc 5 xtal1 period ( 1/f osc ) 50 (see note 6) 1000 (see note 7) ns t xhch xtal1 high to clkout high or low 0 +25 ns t clcl 6 clkout cycle time 2t osc typical ns t chcl 5 clkout high period t osc - 10 t osc +10 ns t cllh clkout falling edge to ale rising -5 +15 ns t llch 5 ale falling edge to clkout rising - 10 +10 ns t lhlh 2 , 6 ale cycle time 4t osc typical ns t lhll 5 ale high period t osc - 10 t osc +15 ns t avll 5 address setup to ale falling edge t osc - 15 ns t llax address hold after ale falling edge t osc - 20 t osc +5 ns t llrl ale falling edge to rd falling edge t osc - 5 t osc +10 ns t rlcl rd low to clkout falling edge -5 +10 ns t rlrh 2 rd low period t osc - 5 ns t rhlh 3,5 rd rising edge to ale rising edge t osc -10 t osc +10 ns t rlaz 5 rd low to address float -5 +5 ns
27 note: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 at 1.0e5 rads(si). 1. if max exceeded, additional wait state occurs. 2. if wait states are used, add 2 t osc *n, where n = number of wait states. 3. assuming back-to-back bus cycles. 4. 8-bit only 5. tested only at initial qualification, and after any design or process changes which may affect this characteristic. 6. these specs are verified using functional vectors (strobed) only. 7. low speed tests performed at 5mhz. 1mhz operation is guaranteed by design. t llwl 5 ale falling edge to wr falling edge t osc - 10 t osc +10 ns t clwl clkout low to wr falling edge -5 +10 ns t qvwh 2 data stable to wr rising edge t osc - 10 t osc +10 ns t chwh 5 clkout high to wr rising edge -10 +15 ns t wlwh 2,5 wr low period t osc - 10 ns t whqx 5 data hold after wr rising edge t osc - 10 t osc +10 ns t whlh 3,5 wr rising edge to ale rising edge t osc - 10 t osc +10 ns t whbx 5 bhe , inst after wr rising edge t osc - 10 t osc +10 ns t whax 4,5 ad8-15 hold after wr rising t osc - 25 ns t rhbx 5 bhe , inst after rd rising edge t osc - 10 t osc +10 ns t rhax 4,5 ad8-15 hold after rd rising t osc - 25 ns t avenv 5 address valid to edacen valid 2t osc -30 ns t lhenx 5 edacen hold after ale high 0 ns t avev 2,5 address valid to edac input valid 3t osc -29 ns t rxex 5 edac hold after rd inactive 0 t osc -10 ns t evwh 2,5 edac output stable to wr rising t osc -10 t osc +10 ns t whex 5 edac output hold after wr rising t osc -10 t osc +10 ns
28 xtal1 clkout read bus write bus bhe, inst ad8-15 t llch t clcl t xhch t chcl t rlcl ale t lhlh t lhll t llrl t rhlh t rlrh t rldv t llax t avll t rlaz t rhdz t osc figure 4. system bus timings address out data t avdv t llwl t wlwh t whlh t whqx t qvwh address out data out address address out valid t whbx, t rhbx t cldv t rxdx t clwl t cllh t chwh t whax, t rhax ecb(5:0) read cycle ecb(5:0) write cycle t avev valid t rxex valid t whex t evwh
29 xtal1 clkout ale ready read bus write bus address out address data out address data t rlrh + 2t osc t wlwh +2t osc t osc t chcl t rldv + 2t osc t avyv t qvwh + 2t osc t avdv + 2t osc t xhch t clcl t lhlh + 2t osc t cllh t llyx max t clyx max t llyx min t clyx min t ylyh figure 5. ready timing (one wait state)
30 figure 6. buswidth and edacen timings clkout ale buswidth bus t clgx xtal1 valid t avgv address out data edacen t avenv valid t lhenx
31 6.0 xtal1 clock drive timing characteristics note: 1. tested only at initial qualification, and after any design or process changes which may affect this characteristic. 2. supplied as a design limit, but not guaranteed or tested. figure 7. external clock drive timing waveforms symbol parameter minimum maximum unit f osc oscillator frequency 1 (note 1) 20 mhz t osc oscillator period 50 1000 (note 1) ns t osch high time 17 (note 1) ns t oscl low time 17 (note 1) ns t oscr rise time 10 (note 2) ns t oscf fall time 10 (note 2) ns t osch t osc t oscf t oscr 0.7 v dd 0.7 v dd 0.3v dd 0.3v dd t oscl 0.7 v dd
32 note: 1.tested only at initial qualification, and after any design or process changes which may affect this characteristic. 7.0 hold / hlda timings note: 1.tested only at initial qualification, and after any design or process changes which may affect this characteristic. table 11. dc specifications in hold description min max conditions pullups on adv , rd , wr , wrl, bhe, ale 6.9k 36.7k v dd =5.5v, v in = v ss pulldown on inst 3.7k 27.5k v dd =5.5v, v in = v dd symbol parameter minimum maximum unit t hvch 1 hold setup 25 ns t clhal 1 clkout low to hlda low -15 15 ns t clbrl 1 clkout low to breq low -15 15 ns t halaz 1 hlda low to address float 10 ns t halbz 1 hlda low to bhe , inst, rd , wr driven weakly 15 ns t clhah 1 clkout low to hlda high -15 15 ns t clbrh 1 clkout low to breq high -15 15 ns t hahax 1 hlda high to address no longer float -15 ns t hahbv 1 hlda high to bhe , inst, rd , wr valid -10 ns t cllh 1 clkout low to ale high -5 15 ns
33 clkout hold hlda breq bus ale/ adv bhe , inst rd , wr t hvch t hvch t clhal t clhah t clbrl t clbrh t hahax t halaz t halbz t hahbv weakly driven inactive t cllh weakly driven high figure 8. dc specifications in hold
34 ut80c196kd xtal1 external clock input figure 9. external clock connections v dd 0.0v 1.4v 1.4v test points ac testing inputs are driven at v dd for a logic ?1? and 0.0v for a logic ?0?. timing measure- ments are made at 1.4v. figure 10. ac testing input, output waveforms v load for timing purposes a port pin is no longer floating when it changes to a voltage outside the ref- erence points shown and begins to float when it changes to a voltage inside the reference points shown. i ol = 4ma, i oh = -4ma. v ol + 0.5v v oh - 0.5v v ol + 0.5v v oh - 0.5v timing reference points figure 11. float waveforms
35 table 12. serial port timing symbol parameter minimum maximum unit t xlxl 2 serial port clock period (brr > 8002h) 6 t osc typical ns t xlxh 1 serial port clock falling edge to rising edge (brr > 8002h) 4 t osc -50 4 t osc +50 ns t xlxl 2 serial port clock period (brr = 8001h) 4 t osc typical ns t xlxh 1 serial port clock falling edge to rising edge (brr = 8001h) 2 t osc -50 2 t osc +50 ns t qvxh 1 output data valid to clock rising edge 2 t osc -50 ns t xhqx 1 output data hold after clock rising edge 2 t osc -50 ns t xhqv 1 next output data valid after clock rising edge 2 t osc +50 ns t dvxh 1 input data setup to clock rising edge t osc +50 ns t xhdx 1 input data hold after clock rising edge 0 ns t xhqz 1 last clock rising to output float 2 t osc -10 2 t osc +10 ns txd rxd (out) rxd (in) 0 1 2 3 4 5 6 7 t xlxl t qvxh t xhqv t xhqx t dvxh t xhdx t xlxh t xhqz figure 12. serial port waveform - shift register mode 0 1 2 3 5 4 6 7 6 note : 1. tested only at initial qualification, and after my design or process changes which may affect this characteristic. 2. these specs are verified functional vectors (strobed) only.
36 appendix a difference between i ndustry standard and ut80c196kd 1.0 ut80c196kd differences to industry standard 80c196kd 1.1 analog to digital converter the analog to digital converter will not be implemented in the ut80c196kd. 1.3 clocking the xtal2 output is not used and the ut80c196kd expects the input on the xtal 1 to be a valid digital clock signal. the clock should be stable before reset is removed or power down mode is exited. in power down mode, a small number of gates will be clocked by the xtal1 input. the ut80c196kd will drive xtal2 low when not in test mode. 1.4 ccb read after reset the ccb fetch after reset will be a normal fetch as if the chosen bus width is selectable based on the buswidth input. systems with an 8-bit wide interface should tie buswidth to ground. systems that use buswidth should perform a normal decode based on the memory configuration of the system. the industry standard 80c196kd treats the ccb fetch as an 8-bit fetch (driving the upper 8-bits with address 20h) regardless of the state of buswidth. 1.5 internal program memory the ut80c196kd does not have internal program memory, and pin 2 (ea) will be ignored for choosing between internal and external program reads. the user may tie this pin to ground for compatibility reasons, unless edac is enabled. 1.6 ports 3 and 4 since the ut80c196kd will not have internal program memory, ports 3 and 4 will always be used as the multiplexed address and data bus. therefore, these ports will not be configured as i/o ports, and the bidirectional port function of these pins will not be implemented. the pins will only be configured as address and bidirectional data pins. 1.7 built in edac the ut80c196kd incorporates a built in error detection and correction circuit for external memory reads and writes. the edac can be controlled from an external pin. the external pin (pin 37) can be used to enable or disable this feature interactively. therefore, different regions of external memory can be assigned to have edac as necessary. additionally, the edac check bits will be passed through port 0, which varies from the industry standard version where port 0 is an input only port. you can control the interrupt behavior of the edac engine by setting bits 6 and 5 of the edac control and status register (edac_cs). additionally, reading bit 4 of the edac_cs allows you to determine if a double bit error occurred, and reading bits 3 through 0 of the edac_cs register tells you how many single bit errors have been corrected. the edac_cs register is located at location 15h of hwindow 1. 1.8 instruction queue the instruction queue is eight bytes deep instead of four. the instruction queue also interfaces to the cpu through a 16-bit bus. this configuration will speed up the operation of the ut80c196kd. 1.9 wdt and prescalar the wdt can now be disabled through the software. the disable feature should allow the user flexibility in using the watch dog timer. the wdt also now has a prescalar which can slow down the counter by a factor of 2 0 to 2 7 . the prescalar will give the user extra time between clears of the wdt. the wdt prescaler (wdt_scale) is located at location 0dh of hwindow 1. 1.10 interrupt priority levels an additional level of priority encoding is available to the user. every standard interrupt can be programed to a higher level of priority. all interrupts in the higher priority will maintain their relative priority, but low priority interrupts can then be programmed for a higher interrupt priority if necessary. the interrupt priority register is 16-bits wide, and maps to the standard interrupts in the same fashion as the int_mask and int_mask1 registers. the high byte of the interrupt priority register (in_pri(hi)) is located at 0bh of hwindow 1, and the low byte (int_pri(lo)) is located at 0ah of hwindow 1. 1.11 faster multiply and divide the multiplier and divider have been optimized to perform their operations in fewer state times than in the current version. 1.12 instructions state time reduction the cpu has been streamlined for faster execution where possible. examples include 1 state reduction for word immediate instructions, 1 state reductions for long indexed instructions, and state reductions for the bmov instructions. 1.13 stack_pntr implemented as special function register the stack_pntr has been implemented as a true special function register instead of in the ram to allow for quicker pushes and pops. if the stack is not used, the sfr can be used for general purpose data storage. 1.14 timer3 an additional 16-bit timer/counter has been implemented as a general purpose timer that can be used if timer1 and timer 2 are being dedicated to other functional uses. the current value
37 of timer3 can be found in locations 0fh (high byte), and 0eh (low byte) of hwindow 1. 1.15 input/output pullup/pulldown currents leakage currents may not meet the industry standard 80c196kd specs due to differently sized weak pullups/ pulldowns, during quasi-bidirectional and reset/powerdown modes. refer to specs for i li1 and i li2 . 1.16 power-down exit pin 37 will not be used to exit power-down mode. since a digital clock is supplied, no connection between this v pp pin and the power-down circuitry exists. 1.17 test mode entry test mode entry will be via four pins: wr, rd , ale and hlda instead of pwm0. 1.18 power-on reset the ut80c196kd will not guarantee the 16-state "pulse stretching" function of a reset_n pulse applied at power-up. the user must hold reset_n low until the power and clocks stabilize plus 16-state times, or provide a high to low transition after the power and clocks have stabilized. 1.19 pullup/pulldown states the inst pin will be driven to a weak low during reset. the ale signal will be driven to a weak high during bus hold. 1.20 modifying the int_pend registers two operand rd-modify-wr instructions should be used to modify the int_pend registers. three operand rd-modify-wr instructions may lose an incoming interrupt. 1.21 serial port synchronous mode the last clock rising edge to output float time (t xhqz ) is made consistent with the output data hold (t xhqx ) time of 2 t osc +/-50nsec. this is longer than the industry standard of 1 t osc max. 1.22 industry standard register indirect with auto incre- ment the industry standard 80c196kd increments the auto-incre- mented register after determining the external address instead of at the end of the instruction completion. the ut80c196kd performs the auto-increment function at the end of the instruc- tion processing. please reference the example below that shows the processing difference between the ut80c196kd and the industry standard 80c196kd: st r0, [r0]+ assume r0 holds the value 1000h before the instruction is exe- cuted. 1.23 ac timing differences there are some ac timing differences between the ut80c196kd and the industry standard 80c196kd. most changes resulted in loosened timing specifications. however, the t rhdz and t rxdx timing specifications were tightened by 5ns. if you have been designing to the industry standard 80c196kd timing specifications, it is important to recognize these two shortened timing specifications. note : please visit the utmc website at www.utmc.com to obtain the latest data sheet updates, application notes, software examples, advisories and erratas for the ut80c196kd. 1.24 t2up-dn input signal port 2.6 has an alternate function of t2up-dn enabled by ioc2.1. the industry standard device appears to allow writes into port 2.6 to directly affect the pin state when in the t2up- dn mode. (this would allow software control of the t2 direc- tion, but requires ensuring a one (qbd pullup) is written to port 2.6 if the pin is driven externally). the ut80c196kd device is designed to disable the port 2.6 output when t2up- dn is enabled. this protects the p2.6/t2up-dn pin from con- tention with an externally driven signal, independent of the value written into port 2. 1.25 neg 8000h instruction operation the ut80crh196kd and the industry standard 80c196kd set the n-flag differently when executing the neg 8000h instruction. neg represents the mcs-96 opcode to negate a defined operand (8000h). when the ut80crh196kd exe- cutes the neg 8000h instruction, the result becomes 8000h with both the n-flag and the v-flag set. the industry stan- dard 80c196kd, however, executes the neg 8000h instruc- tion with a result of 8000h and only the v-flag set. processing flow for the st r0, [r0]+ instruction ut80c196kd industry standard 80c196kd address = [r0]; 1000h address = [r0]; 1000h r0 ---> address r0 = r0+1; 1001h r0 = r0+1; 1001h r0 ---> address * the contents in address 1000h are 1000h * the contents in address 1000h are 1001h
38 1.26 reserved opcode eeh the industry standard 80c196kd using the mcs-96 isa declares the opcode eeh as a reserved opcode and does not guarantee the generation of the unimplemented opcode inter- rupt. the ut80crh196kd, on the other hand, generates the unimplemented opcode interrupt when the eeh opcode is executed. 1.27 byte-wide reads of the hsi_time sfr in order to ensure that the next hsi event is loaded from the fifo into the hsi holding register, the hsi_time special function register must be read as a 16-bit word. byte-wide reads of the hsi_time register will not result in successful loading of the hsi holding register. 1.28 bmov and bmovi maximum count limitation the bmov and bmovi instructions provide a powerful method to transferring a large block of data from one location in memory to another. the syntax for the bmov and bmovi instructions are as follows: bmov src_dest_reg, cntreg bmovi src_dest_reg, cntreg the src_dest_reg is a long register that contains both addresses for the source and destination blocks. the cntreg is a 16-bit register specifying the number of transfers being performed. unlike the industry standard 80c196kd which will accept any 16-bit counter value, the ut80c196kd will only accept a value in the range of 0000h to 3fffh. 1.29 breq activation prior to hlda the breq signal is used by the ut80c196kd to signal a dma arbiter that it would like to recover access to the mem- ory bus. the ut80c196kd, on the other hand, uses the hlda signal to provide confirmation to the dma arbiter that the ut80c196kd has relinquished control of the memory bus. if the wait state control signal (ready) is high when the ut80c196kd decides it will release the bus based on the assertion of the hold signal, it will drive the breq low one clkout cycle ahead of its assertion of the hlda . con- versely, if the ready signal is low when the ut80c196kd decides to relinquish the bus, it will assert breq coincidently with hlda or some clkout cycle later. the latter behavior is compatible with the industry standard 80c196kd function- ality, but the former is unique to the ut80c196kd. 1.30 hold must be synchronized with clkout the dma arbiter must synchronize the hold signal with the clkout on the ut80c196kd. the timing diagram in fig- ure 8 eludes to the synchronicity of the hold signal, but does not clearly identify the outcome if the hold signal does not satisfy the timing parameter t hvch . if the hold setup time is violated on the industry standard 80c196kd, it will require one additional clkout cycle before it recognizes the state change of hold . violating the hold setup time on the ut80c196kd will result in a metastable condition and the ut80c196kd?s reaction is undefined.
39 8.0 package notes: 1. all package finishes are per mil-prf-38535. 2. letter designations are for cross-reference to mil-std-1835. 3. all leads increase max. limit by 0.003 measured at the center of the flat, when lead finish a (solder) is applied. 4. id mark: configuration is optional. 5. lettering is not subject to marking criteria. 6. total weight is approx. 8.0 grams. figure 12. 68-lead quad flatpack
40 ordering information ut80c196kd 16-bit microcontroller: smd lead finish: (note 1, 2) (a) = solder (c) = gold (x) = optional case outline: (x) = 68-lead top brazed flatpack class designator: (q) = class q device type (01) = 20 mhz, 16-bit microcontroller (02) = 20 mhz, 16-bit microcontroller, extended industrial temp (-40 o c to +125 o c) drawing number: 98583 total dose: none federal stock class designator: no options 5962 - 98583 01 * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an ?x? is specified when ordering, part number will match the lead finish and will be either ?a? (solder) or ?c? (gold).
41 ut80c196kd microcontroller ut80c196kd - * * * lead finish: (note 1, 2) (a) = solder (c) = gold (x) = optional screening: (note 3, 4, 5) (c) = mil temp (p) = prototype (w) = extended industrial temp (-40 o c to +125 o c) package type: (w) = 68-lead top brazed flatpack utmc core part number notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part number will match the lead finish and will be either ?a? (solder) or ?c? (go ld). 3. military temperature range flow per utmc manufacturing flows document. devices are tested -55c, room temp, and 125c. 4. prototype flow per utmc manufacturing flows document tested at 25c only. lead finish is gold only. 5. extended industrial temperature range flow per utmc manufacturing flows document. devices are tested at -40 o c, room temp, and +125 o c. radiation is neither tested nor guaranteed.
42 notes
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